21209 ms pc 20080722-s00003 no.a1277-1/9 specifications of any and all sanyo semiconductor co.,l td. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer ' s products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer ' sproductsor equipment. any and all sanyo semiconductor co.,ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, av equipment, communication device, office equipment, industrial equ ipment etc.). the products mentioned herein shall not be intended for use for any "special application" (medica l equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, t ransportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of re liability and can directly threaten human lives in case of failure or malfunction of the product or may cause har m to human bodies, nor shall they grant any guarantee thereof. if you should intend to use our products for app lications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. if there is n o consultation or inquiry before the intended use, our customer shall be solely responsible for the use. LV5256GP overview the LV5256GP is an operating mode switching type step-up/step-down converter that can switch the operating mode by using the external signal. functions ? built-in pch gate drive power supply ? output short-circuit detection by monitoring the input side of the error amplifier ? ocp timer function ? software start function ? support for tracking function ? built-in thermal protection circuit ? built-in uvlo ? on/off function: off-time input current smaller than 1 a ? oscillation frequency : 300khz to 1.5mhz oscillation frequency can be set by an external resistor specifications maximum ratings at ta = 25 c parameter symbol conditions ratings unit maximum input voltage v in max 12 v v dd max 3.6 v maximum output voltage v o max 16 v maximum output current i o max between out and sw 650 ma allowable input pin voltage v cont max rt, fb, in, ocp, ss, onoff, trac_in, du_sel, opc_sel pins v dd v allowable power dissipation pd max mounted on a specified board * 0.8 w operating temperature topr -20 to +85 c storage temperature tstg -40 to +125 c * specified board : 50mm 40mm 0.8mm, glass epoxy 4-layer circuit board (2s2p). bi-cmos lsi operating mode switching type step-up/down converter orderin g numbe r : ena1277
LV5256GP no.a1277-2/9 recommended operating conditions at ta = 25c parameter symbol conditions ratings unit v in 4.5 to 10 v input voltage range v dd 2.9 to 3.1 v v1 when in normal operation mode 1.0 to v in v step-down v2 when in tracking operation mode 0 to v in v v out 1 when in normal operation mode 5.3 to 14 v output voltage range step-up v out 2 when in tracking operation mode v in to v output current io 600 ma electrical characteristics at ta = 25c, v dd = 3.0v, v in = 6.0v ratings parameter symbol conditions min typ max unit reference voltage reference voltage for comparison vref -1% 1.0 -1% v error amplifier input voltage range vrange 0 1.5 v open loop voltage gain av 60 110 db unity-gain bandwidth ft 2 8 mhz output source current ifbol in = 2.0v, fb = 1.0v 2 ma output sink current ifboh in = 0v, fb = 0v 100 a in pin source current iinil in = 0v 100 300 na fb pin output range r_fb 0.1 v trac_in pin source current itracl in = 0 to vref 100 300 na trac_in pin input operation r ange r_trac 0.1 vref-0.1 v logic input pin block 1 (onoff) input voltage h level vonih 2.8 v input voltage l level vonil 0.5 v input current h level ionih onoff = 3.3v 0 a input current l level ionil onoff = 0v 0 a logic input pin block 2 (du_sel) input voltage h level vduih 2.8 v input voltage l level vduil 0.5 v input pull-down resistance rdu 200 k ? logic input pin block 3 (ocp_sel) input voltage h level vocpih 2.8 v input voltage l level vocpil 0.5 v input pull-down resistance rocp 100 k ? soft start soft start source current issh ss = 0v 7 10 13 a soft start sink current issl w hen reset, ss = 1.0v 1 ma short-circuit protection, scp short-circuit protection detection voltage 1 vsc1 ocp_sel=gnd/open *1 0.8 v short-circuit protection detection voltage 2 vsc2 ocp_sel=reg_0 *1 0.4 v scp comparator offset voltage sc posf trac_in = 0.7v, operation starts from 0.9v. -40 40 mv ocp pin source current iocph when in sh ort-circuit protection detection mode 10 a ocp pin sink current iocpl when in norma l operation mode, ocp = 1.0v 0.3 1 3 ma ocp timer latch voltage vocp 1.1 1.2 1.3 v continued on next page.
LV5256GP no.a1277-3/9 continued from preceding page. ratings parameter symbol conditions min typ max unit therml protection, uvlo thermal protection operating temperature tot design guarantee value *2 175 c thermal protection hysteresis dot design guarantee value *2 20 c uvlo lock release voltage 1 vuvloh reg_o monitored 2.8 v uvlo lock voltage 1 vuvlol reg_o monitored 2.5 v uvlo lock release voltage 2 vuvloh2 v in pin voltage 3.8 v uvlo lock voltage 2 vuvlol2 v in pin voltage 3.5 v oscillator oscillation frequency f rt = 100k ? 0.8 1 1.2 mhz oscillation frequency range r_f 0.3 1.5 mhz triangular wave lower-side threshold value vtril rt = 100k ? 0.5 v triangular wave upper-side threshold value vtrih rt = 100k ? 1.0 v power supply pin block ivin1 v in pin, when converter is in 1mhz operation mode. 2 4 ma ivin2 v in pin, when in onoff stop mode. 1.0 a current drain ivdd1 v dd pin, when in onoff stop mode. 1.0 a vout-5v regulator output voltage voutm5 vout-5v regulator, vout = 10.0v vout-4.5 vout-5 vout-5.5 v drooping current ivoutm5 vout-5v regulator 20 ma internal 3.3v regulator output voltage vreg_o ireg_o = 2.0ma 3.0 3.3 3.6 v drooping current ireg_o vreg_o = 2v, v in = 5v 10 ma output characteristics main switch on resistance (pch) ronh v in = 5v 0.7 ? main switch on resi stance (nch) ronl v in = 5v 0.7 ? through current prevention dead time tdead 25 ns maximum on-duty (step-down) dmax1 rt = 100k ? 100 % maximum on-duty (step-up) dmax2 rt = 100k ? 85 % converter characteristics step-down 1 v in = 5.0v, v = 4.6v, i o = 200ma 93 % efficiency step-up 2 v in = 5.0v, vout1 = 6.6v, i o = 200ma 93 % step-down ? v1/v in v in = 4.5 to 8.6v, v1 = 4.6v, i o = 200ma 0 % line regulation step-up ? vout1/v in v in = 4.5 to 5.5v, vout1 = 6.6v, i o = 200ma 0 % step-down ? v1/i o v in = 8.4v, v1 = 4.6v, i o = 0 to 200ma 0 load regulation step-up ? vout1/i o v in = 5.0, vout1 = 6.6v, i o = 200ma 0 *1 in pin voltage is the detection point. the lowest voltage among vref, trac _in, and ss is used. *2 design guarantee value, and no measurement is performed.
LV5256GP no.a1277-4/9 package dimensions unit : mm (typ) 3368 pin assignment 1 top view nc 2 3 4 5 6 7 8 12 11 10 9 16 15 14 13 20 19 18 17 nc nc onoff vin du_sel pgnd sw vout vout-5 ocp reg_o ss trac_in fb in ocp_sel rt v dd lgnd LV5256GP sanyo : vct20(3.0x3.0) 0.4 3.0 3.0 0.8 (0.035) top view side view side view bottom view 0.25 0.5 (0.5) (c0.17) 12 20 (0.125) (0.13) pd max -- ta ambient temperature, ta ? c allowable power dissipation, pd max ? w ? 20 0 20 40 60 80 100 0 1.0 0.8 0.6 0.4 0.2 0.32 mounted on a specified board : 50 400.8mm 3 glass epoxy 4-layer circuit board (2s2p)
LV5256GP no.a1277-5/9 block diagrams and sample application circuit 1 (step-down) bias vref tsd disable ot vref (1.0v1%) vref1r2 (1.2v) vreg uvlo 3.3v disable 2.8v/2.5v uvlo osc 0.5v 1.0v + + + + + du_sel disable ot uvlo tout pwm control logic l/s + disable uvlo vrefr2 r sq tout disable uvlo + + + vref + vref1r2 disable l/s vreg vout-5 vout-5 vdd pin heap 17 pin fb 0.8 0.4 in v1 or v2 ocp gnd/ open 0.01f at 1.25ms du_sel opc_sel gnd/open: 0.8 reg_o: 0.4 0.033f at 3.3ms trac_in ss onoff v dd 0.1f v dd =2.9 to 3.1v lgnd sbd 22h pgnd sw 4.7f vout vout-5 1f vin vin=4.5 to 10v reg_o rt 0.1f 100k at 1mhz 0.022f du_sel v1 (normal operation) =1.0v to vin v2 (tracking operaton) =0v to vin ldo with opc sample application circuit 2 (step-up) bias vref tsd disable ot vref (1.0v1%) vref1r2 (1.2v) vreg uvlo 3.3v disable 2.8v/2.5v uvlo osc 0.5v 1.0v + + + + + du_sel disable ot uvlo tout pwm control logic l/s + disable uvlo vrefr2 r sq tout disable uvlo + + + vref + vref1r2 disable l/s vreg vout-5 vout-5 vdd pin heap 17 pin fb 0.8 0.4 in vout1 or vout2 ocp reg_o 0.01f at 1.25ms du_sel opc_sel gnd/open: 0.8 reg_o: 0.4 0.033f at 3.3ms trac_in ss onoff v dd 0.1f v dd =2.9~3.1v lgnd 10h pgnd sw vout vout-5 1f vin vin=4.5~10v reg_o rt 0.1f 100k at 1mhz 0.022f 4.7f du_sel vout1 (normal operation) =5.3v to 14v vout2 (tracking operaton) =vin or more ldo with opc
LV5256GP no.a1277-6/9 pin functions pin no. pin name description equivalent circuit 1 2 6 nc no connection. must be kept open. 3 onoff on/off signal input pin. threshold level is ttl level. maximum withstand voltage is v dd. 3 v dd 4 vin power supply pin of the ic. apply the input voltage. 5 du_sle step-up/down switching pin. the ic goes in step-up mode by connecting this pin to reg_o pin, and in step-down mode by connecting this pin to gnd or leaving this pin open. an internal pull-down resistor (200k ? ) is provided between du_sel and gnd pins. 5 v dd 200k? 7 pgnd power ground pin. the source of the output transistor (nch-mosfet) is connected. 8 sw switching element. a 0.7 ? (typ) nch switch is inserted between this pin and pgnd, and a 0.7 ? (typ) pch switch is connected between this pin and vout. in step-down mode, insert an inductor between the switching node and power supply output, and in step-up mode insert an inductor between this pin and power supply input. 8 vout 9 vout source potential of the internal pch-mosfet. in step-down mode, apply the inpu t voltage. in step-up mode, apply the power supply voltage. 10 vout-5 internal pch-mosfet gate suplly voltage generation pin. used to generate a voltage with a level equal to vout pin voltage-5v by the internal ldo with ocp. 11 ocp overcurrent detection timer setup pin. connect a capacitor between this pin and ground to define the time interval between the beginning of the overcurrent state and the ic latches off. the capacitor is charged by the 10 a internal constant current source. if the ocp_sel pin is kept open or connected to gnd, the ic identifies a short-circuit and starts the timer counter when the voltage at the in pin falls below 0.8 times the voltage of vref, trac_in or ss, whichever is lower. if the ocp_sel pin is connected to reg_o, the ic compares the vo ltage at the in pin with 0.4 times the voltage. when the voltage at this pin goes beyond 1.25v, the ic latches of f. the latch-off state is reset by the off signal at the on/off pin or the uvlo lock. 11 vin 500? reg_o 1k? 10k? 10a 12 reg_o 3.3v regulator output pin. 12 vin 50? 32k? 20k? continued on next page.
LV5256GP no.a1277-7/9 continued from preceding page. pin no. pin name description equivalent circuit 13 ss capacitor connection pin fo r soft start. the capacitor connected to this pin is charged by the internal 10 a constant current. the interval during which this voltage reaches vref is called the soft start period. the voltage is clipped to approx. 2v after the soft start. this pin is pulled down to the ground level when onoff/uvlo lock mode. 13 vin 500? reg_o 10k? 10a 1.25v reg_o 14 trac_in reference voltage input pin for tracking power supply operating. a voltage from 0v up to vref applied to this pin serves as the reference voltage for determining the output voltage. this pin must be connected to the ss pin when it is not to be used. 14 vin 1k? reg_o reg_o 15 fb error amplifier output pi n. connect a phase compensation component between this pin and in pin. 15 vin 1k? 1.25v reg_o 400? 100a 16 in output voltage input pin. apply the resistor divided output voltage to this pin. reg_o 16 vin 1k? ss trac_in vre f reg_o 17 ocp_sel ocp detection voltage switching pin, a 100k ? pull-down resistor is provided between ocp_sel and gnd. the ic enters the 0.8 times detection mode when this pin is connected to gnd or kept open and enters the 0.4 times detection mode when the pin is connected to the reg_o pin. 17 v dd 100k? continued on next page.
LV5256GP no.a1277-8/9 continued from preceding page. pin no. pin name description equivalent circuit 18 rt oscillation frequency sett ing pin. connect a resistor between this pin and gnd. a 100k ? resistor causes the oscillator to oscillat e at 1mhz (typ.). 18 v dd 10k? 500? 19 v dd logic system power supply. apply 3.0v 0.1v to this pin from an external source. 20 lgnd logic system ground pin. all voltages are measured with respect to this voltage level. startup sequence onoff vin reg_o vout-5 ss sw onoff:h reg_o startup uvlo release vout-5 startup vout-5 normal judgment ss start power supply operation beginning v dd * be sure to set the onoff to 0v when starts or stops v dd . and apply voltage to vin after v dd started up.
LV5256GP ps no.a1277-9/9 sanyo semiconductor co.,ltd. assumes no responsib ility for equipment failures that result from using products at values that exceed, even momentarily, rate d values (such as maximum ra tings, operating condition ranges, or other parameters) listed in products specif ications of any and all sanyo semiconductor co.,ltd. products described or contained herein. sanyo semiconductor co.,ltd. strives to supply high-qual ity high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. it is possible that these probabilistic failures or malfunction could give rise to acci dents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause dam age to other property. when designing equipment, adopt safety measures so that these kinds of accidents or e vents cannot occur. such measures include but are not limited to protective circuits and error prevention c ircuits for safe design, redundant design, and structural design. upon using the technical information or products descri bed herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of sanyo semiconductor co.,ltd. or any third party. sanyo semiconductor co.,ltd. shall not be liable f or any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. information (including circuit diagr ams and circuit parameters) herein is for example only; it is not guaranteed for volume production. any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. when designing equi pment, refer to the "delivery specification" for the sanyo semiconductor co.,ltd. product that you intend to use. in the event that any or all sanyo semiconductor c o.,ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities conc erned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any in formation storage or retrieval system, or otherwise, without the prior written consent of sanyo semiconductor co.,ltd. output voltage setting method the LV5256GP can produce any arbitrary output voltage. the output voltage is set by the resistor inserted between the in pin (pin 16) and gnd, and in pin and output voltage. the calculating formula for setting the output voltage by using the output voltage setup lower-side resistor r1 and the output voltage setup upper-side resistor r2 is as follows: in r1 r2 output voltage (step-down) v1 or v2 (step-up) vout1 or vout2 this catalog provides information as of february, 2 009. specifications and information herein are subject to change without notice. )(00.1 1 2 1 1 2 1) ( typ vref r r vref r r voltage output = += ? ? ? ? ? ? += q
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